參數(shù)資料
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Interrupts
General Release Specification
MC68HC05C12A — Rev. 3.0
36
Interrupts
MOTOROLA
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but they are considered pending until the current
instruction is complete.
NOTE:
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-
bit state.
Vector addresses for all interrupts, including reset, are listed in
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
Interrupts
CPU
Interrupt
Vector
Address
N/A
Reset
RESET
$3FFE–$3FFF
N/A
Software
SWI
$3FFC–$3FFD
N/A
External Interrupt
IRQ
$3FFA–$3FFB
TSR
ICF
Timer Input Capture
TIMER
$3FF8–$3FF9
TSR
OCF
Timer Output
Compare
TIMER
$3FF8–$3FF9
TSR
TOF
Timer Overow
TIMER
$3FF8–$3FF9
SCSR
TDRE
Transmit Buffer
Empty
SCI
$3FF6–$3FF7
SCSR
TC
Transmit Complete
SCI
$3FF6–$3FF7
SCSR
RDRF
Receiver Buffer Full
SCI
$3FF6–$3FF7
SCSR
IDLE
Idle Line Detect
SCI
$3FF6–$3FF7
SCSR
OR
Overrun
SCI
$3FF6–$3FF7
SPSR
SPIF
Transfer Complete
SPI
$3FF4–$3FF5
SPSR
MODF
Mode Fault
SPI
$3FF4–$3FF5
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