參數(shù)資料
型號(hào): MC68HSC05C12ACFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 131/156頁
文件大小: 756K
代理商: MC68HSC05C12ACFN
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Communications Interface (SCI)
General Release Specification
MC68HC05C12A Rev. 3.0
76
Serial Communications Interface (SCI)
MOTOROLA
9.6.4 SCI Status Register
The SCI status register contains flags to signal the following conditions:
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
TDRE — Transmit Data Register Empty
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set, and then writing to the SCDR.
Reset sets the TDRE bit. Software must initialize the TDRE bit to logic
zero to avoid an instant interrupt request when turning on the
transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete
This clearable, read-only bit is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
Address:
$0010
Bit 7
654321
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
Write:
Reset:
00000000
Figure 9-7. SCI Status Register (SCSR)
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