
Memory
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
28
Memory
MOTOROLA
$0027
TIM Channel 0
Register Low (TCH0L)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
Indeterminate after reset
$0028
TIM Channel 1 Status and
Control Register (TSC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
00000000
$0029
TIM Channel 1
Register High (TCH1H)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
$002A
TIM Channel 1
Register Low (TCH1L)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
Indeterminate after reset
$002B
↓
$0035
Unimplemented
$0036
Oscillator Status Register
(OSCSTAT)
Read:
RRRRRR
ECGON
ECGST
Write:
Reset:
00000000
$0037
Unimplemented Read:
$0038
Oscillator Trim Register
(OSCTRIM)
Read:
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
TRIM0
Write:
Reset:
10000000
$0039
↓
$003B
Unimplemented
$003C
ADC Status and Control
Register (ADSCR)
Read:
COCO
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
Write:
Reset:
00011111
$003D
Unimplemented
$003E
ADC Data Register
(ADR)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)