
Operating Modes and On-Chip Memory
Memory Map
MC68HC11E Family — Rev. 4
Technical Data
MOTOROLA
Operating Modes and On-Chip Memory
87
Address:
$103F
Bit 7
654321
Bit 0
Read:
NOSEC
NOCOP
ROMON
EEON
Write:
Resets:
Single chip:
0000
U
1
U
Bootstrap:
0000
U
U(L)
U
Expanded:
00001
U
Test:
00001
U(L)
U
= Unimplemented
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch
prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register.
Figure 4-10. System Configuration Register (CONFIG)
Address:
$103F
Bit 7
654321
Bit 0
Read:
EE3
EE2
EE1
EE0
NOSEC
NOCOP
EEON
Write:
Resets:
Single chip:
1111
U
11
Bootstrap:
1111
U
U(L)
1
Expanded:
UUUU
1
U
1
U
Test:
UUUU
1
U(L)
1
0
= Unimplemented
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch
prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register.
Figure 4-11. MC68HC811E2 System Configuration Register (CONFIG)