MOTOROLA
30
MC68HC11A8
MC68HC11A8TS/D
DDD[5:0] — Data Direction for Port D
When DDRD bit 5 is zero and MSTR = 1 in SPCR, PD5/SS is a general-purpose output and mode fault
logic is disabled.
0 = Input
1 = Output
SPIE — Serial Peripheral Interrupt Enable
0 = SPI interrupts disabled
1 = SPI interrupts enabled
SPE — Serial Peripheral System Enable
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode
DWOM affects all six port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL, CPHA — Clock Polarity, Clock Phase
Refer to Figure 10
Figure 10 SPI Transfer Format
SPCR
— Serial Peripheral Control Register
$1028
Bit 7
SPIE
0
6
5
4
3
2
1
Bit 0
SPR0
U
SPE
0
DWOM
0
MSTR
0
CPOL
0
CPHA
1
SPR1
U
RESET:
SPI TRANSFER FORMAT 1
2
3
4
5
6
7
8
1
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK CYCLE #
SS (TO SLAVE)
6
5
4
3
2
1
LSB
MSB
MSB
6
5
4
3
2
1
LSB
1
2
3
5
4
SLAVE CPHA=1 TRANSFER IN PROGRESS
MASTER TRANSFER IN PROGRESS
SLAVE CPHA=0 TRANSFER IN PROGRESS
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
SAMPLE INPUT
DATA OUT
(CPHA = 0)
SAMPLE INPUT
DATA OUT
(CPHA = 1)
