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ELECTRICAL CHARACTERISTICS
MC68HC11A8
A-16
TECHNICAL DATA
A
Figure A-13 Three-State Variation of Output Handshake Timing Diagram
(STRA Enables Output Buffer)
E
tDEB
PORT C (OUT)
(DDR = 1)
READ PORTCL1
STRB (OUT)
tPWD
"READY"
NOTES:
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
tAES
OLD DATA
NEW DATA VALID
PORT C (OUT)
(DDR = 0)
STRA (IN)
a) STRA ACTIVE BEFORE PORTCL WRITE
NEW DATA VALID
PORT C (OUT)
(DDR = 0)
STRA (IN)
b) STRA ACTIVE AFTER PORTCL WRITE
tDEB
tPCZ
tPCH
tPCZ
tPCH
tPCD
t PCD
3STATE VAR HNDSHK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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