參數(shù)資料
型號(hào)： MC68HCL05C8FB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 144/156頁
文件大?。?/td> 1755K
代理商： MC68HCL05C8FB
Serial Peripheral Interface (SPI)
Advance Information
MC68HC05C8A — Rev. 4.0
88
Serial Peripheral Interface (SPI)
MOTOROLA
10.4.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the
transaction.
The SS line on the master must be tied high. If it goes low, a mode fault
error flag (MODF) is set in the SPSR.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line
could be tied to VSS as long as CPHA = 1 clock modes are used.
10.5 Functional Description
Figure 10-2 shows a block diagram of the SPI circuitry. When a master
device transmits data to a slave via the MOSI line, the slave device
responds by sending data to the master device via the master’s MISO
line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is
replaced by the byte received and eliminates the need for separate
transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the input/output (I/O) operation has been completed.
The SPI data register (SPDR) is double buffered on read, but not on
write. If a write is performed during data transfer, the transfer occurs
uninterrupted, and the write will be unsuccessful. This condition will
cause the write collision (WCOL) status bit in the SPSR to be set. After
a data byte is shifted, the SPIF flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
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