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| 型號(hào)： | MC68HC912BL16FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 115/128頁(yè) |
| 文件大?。?/td> | 532K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16
MOTOROLA
MC68HC912BL16TS/D
87
13 Serial Interface
The serial interface of the MC68HC912BL16 consists of two independent serial I/O sub-systems: the
serial communication interface (SCI) and the serial peripheral interface (SPI). Each serial pin shares
function with the general-purpose port pins of port S. The SCI is an NRZ type system that is compatible
with standard RS-232 systems. The SCI system has a single wire operation mode which allows the un-
used pin to be available as general-purpose I/O. The SPI subsystem, which is compatible with the
M68HC11 SPI, includes new features such as SS output and bidirectional mode.
13.1 Block Diagram
Figure 21 Serial Interface Block Diagram
13.2 Serial Communication Interface (SCI)
The serial communication interface on the MC68HC912BL16 is an NRZ format (one start, eight or nine
data, and one stop bit) asynchronous communication system with independent internal baud rate gen-
eration circuitry and an SCI transmitter and receiver. It can be configured for eight or nine data bits (one
of which may be designated as a parity bit, odd or even). If enabled, parity is generated in hardware for
transmitted and received data. Receiver parity errors are flagged in hardware. The baud rate generator
is based on a modulus counter, allowing flexibility in choosing baud rates. There is a receiver wake-up
feature, an idle line detect feature, a loop-back mode, and various error detection features. Two port
pins provide the external interface for the transmitted data (TXD) and the received data (RXD).
SCI
SPI
SERIAL
HC12BL16 SI BLOCK
INTERFACE
PS0
PS1
PS4
PS5
PS6
PS7
RxD
TxD
MISO/SISO
MOSI/MOMI
SCK
CS/SS
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