
System Integration Module (SIM)
Reset and System Initialization
MC68HC908QY/QT Family — Rev. 3
Data Sheet
MOTOROLA
System Integration Module (SIM)
117
13.4 Reset and System Initialization
The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor
mode) and assert the internal reset signal (IRST). IRST causes all registers to be
returned to their default values and all modules to be returned to their reset states.
An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external
reset does not. Each of the resets sets a corresponding bit in the SIM reset status
13.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the asynchronous
RST pin low halts all processing. The PIN bit of the SIM reset status register
(SRSR) is set as long as RST is held low for at least the minimum tRL time.
Figure 13-4 shows the relative timing. The RST pin function is only available if the
RSTEN bit is set in the CONFIG1 register.
Figure 13-4. External Reset Timing
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the
RSTEN bit in the CONFIG1 register enables the pin for the reset function. This
section assumes the RSTEN bit is set when describing activity on the RST pin.
NOTE:
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles during
which the SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST shown in Figure 13-5.
The COP reset is asynchronous to the bus clock.
RST
ADDRESS BUS
PC
VECT H
VECT L
BUSCLKX2
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