- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗3794 > MC68HC908QY1CDW (Freescale Semiconductor)IC MCU 1.5K FLASH 16-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC68HC908QY1CDW |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 115/184闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 1.5K FLASH 16-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 47 |
| 绯诲垪锛� | HC08 |
| 鏍稿績铏曠悊鍣細 | HC08 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 8MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | LVD锛孭OR锛孭WM |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 13 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 1.5KB锛�1.5K x 8锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
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Memory
MC68HC908QY/QT Family Data Sheet, Rev. 6
36
Freescale Semiconductor
8.
Wait for time, tPROG (minimum 30 渭s).
9.
Repeat step 7 and 8 until all desired bytes within the row are programmed.
10.
Clear the PGM bit(1).
11.
Wait for time, tNVH (minimum 5 渭s).
12.
Clear the HVEN bit.
13.
After time, tRCV (typical 1 渭s), the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between
steps 5鈥�12, when the HVEN bit is set. Since this register is located at a
valid FLASH address, unpredictable behavior may occur if this location is
written while HVEN is set.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect blocks of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1鈥檚), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are
shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass
erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be
erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also
allows entry from reset into the monitor mode.
2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing
PGM bit, must not exceed the maximum programming time, tPROG maximum.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MC68HC908QY1CP | IC MCU 1.5K FLASH 16-DIP |
| MC68HC908QT4CDW | IC MCU 4K FLASH W/ADC 8-SOIC |
| MC68HC908QT4CP | IC MCU 4K FLASH W/ADC 8-DIP |
| MC68HC908QT2CDW | IC MCU 1.5K FLASH W/ADC 8-SOIC |
| MC68HC908QT2CP | IC MCU 1.5K FLASH W/ADC 8-DIP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC68HC908QY1CP | 鍔熻兘鎻忚堪:IC MCU 1.5K FLASH 16-DIP RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:HC08 鍏跺畠鏈夐棞(gu膩n)鏂囦欢:STM32F101T8 View All Specifications 鐗硅壊鐢�(ch菐n)鍝�:STM32 32-bit Cortex MCUs 妯�(bi膩o)婧�(zh菙n)鍖呰:490 绯诲垪:STM32 F1 鏍稿績铏曠悊鍣�:ARM? Cortex?-M3 鑺珨灏哄:32-浣� 閫熷害:36MHz 閫ｉ€氭€�:I²C锛孖rDA锛孡IN锛孲PI锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:DMA锛孭DR锛孭OR锛孭VD锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):26 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲�:64KB锛�64K x 8锛� 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:10K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 10x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:36-VFQFN锛�36-VFQFPN 鍖呰:鎵樼洡(p谩n) 閰嶇敤:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2鏇村... 鍏跺畠鍚嶇ū(ch膿ng):497-9032STM32F101T8U6-ND |
| MC68HC908QY1CPE | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.5K FLASH W/O AD-LEAD RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MC68HC908QY1MDT | 鍒堕€犲晢:Motorola Inc 鍔熻兘鎻忚堪: 鍒堕€犲晢:MOTOROLA 鍔熻兘鎻忚堪: |
| MC68HC908QY1MDTE | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.5K FLASH W/O ADC RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| MC68HC908QY1MDW | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8 Bit 8MHz RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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