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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC68HC908LJ12CFU
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 230/414闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 12K FLASH 8MHZ 64-QFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 84
绯诲垪锛� HC08
鏍稿績铏曠悊鍣細 HC08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
閫i€氭€э細 IRSCI锛孲PI
澶栧湇瑷�(sh猫)鍌欙細 LCD锛孡VD锛孭OR锛孭WM
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 12KB锛�12K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 6x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-QFP
鍖呰锛� 鎵樼洡
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Analog-to-Digital Converter (ADC)
MC68HC908LJ12 鈥� Rev. 2.1
Technical Data
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
305
15.4.2 Voltage Conversion
When the input voltage to the ADC equals VREFH, the ADC converts the
signal to $3FF (full scale). If the input voltage equals VREFL, the ADC
converts it to $000. Input voltages between VREFH and VREFL are
straight-line linear conversions. All other input voltages will result in
$3FF if greater than VREFH and $000 if less than VREFL.
NOTE:
Input voltage should not exceed the analog supply voltages.
15.4.3 Conversion Time
Conversion starts after a write to the ADSCR. A conversion is between
16 and 17 ADC clock cycles, therefore:
The ADC conversion time is determined by the clock source chosen and
the divide ratio selected. The clock source is either the bus clock or
CGMXCLK and is selectable by the ADICLK bit located in the ADC clock
register. The divide ratio is selected by the ADIV[2:0] bits.
For example, if a 4MHz CGMXCLK is selected as the ADC input clock
source, with a divide-by-2 prescale, and the bus speed is set at 8MHz:
NOTE:
The ADC frequency must be between fADIC minimum and fADIC
maximum to meet ADC specifications. See 23.6 5.0V DC Electrical
Since an ADC cycle may be comprised of several bus cycles (eight in the
previous example) and the start of a conversion is initiated by a bus cycle
write to the ADSCR, from zero to four additional bus cycles may occur
before the start of the initial ADC cycle. This results in a fractional ADC
cycle and is represented as the 17th cycle.
16 to17 ADC cycles
Conversion time =
ADC frequency
Number of bus cycles = conversion time
脳 bus frequency
16 to 17 ADC cycles
Conversion time =
4MHz
梅 2
Number of bus cycles = 8
s x 8MHz = 64 to 68 cycles
= 8 to 8.5
s
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
MC68HC908LJ24CFQ 鍔熻兘鎻忚堪:IC MCU 24K FLASH 8MHZ SPI 80-QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:HC08 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:56F8xxx 鏍稿績铏曠悊鍣�:56800E 鑺珨灏哄:16-浣� 閫熷害:60MHz 閫i€氭€�:CAN锛孲CI锛孲PI 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):21 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲�:40KB锛�20K x 16锛� 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:6K x 16 闆诲 - 闆绘簮 (Vcc/Vdd):2.25 V ~ 3.6 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 6x12b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:48-LQFP 鍖呰:鎵樼洡 閰嶇敤:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
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MC68HC908LJ24CFU 鍒堕€犲晢:FREESCALE SEMICONDUCTOR 鍔熻兘鎻忚堪:_
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