
SIM Registers
MC68HC908GR8 MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
201
Figure 19-18. Stop Mode Entry Timing
Figure 19-19. Stop Mode Recovery from Interrupt or Break
19.7 SIM Registers
The SIM has three memory-mapped registers.
Table 19-4 shows the mapping of these registers.
19.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode
Table 19-4. SIM Registers
Address
Register
Access Mode
$FE00
SBSR
User
$FE01
SRSR
User
$FE03
SBFCR
User
Address:
$FE00
Bit 7
654321
Bit 0
Read:
RRRRRR
BW
R
Write:
Note(1)
Reset:
00000000
R= Reserved
Note: 1. Writing a logic 0 clears SBSW.
Figure 19-20. SIM Break Status Register (SBSR)
STOP ADDR + 1
SAME
IAB
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
STOP ADDR
SAME
R/W
CPUSTOP
Note : Previous data can be operand data or the STOP opcode, depending
on the last instruction.
CGMXCLK
INT/BREAK
IAB
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
STOP RECOVERY PERIOD