
Input/Output (I/O) Section
MC68HC908EY16A MC68HC908EY8A Data Sheet, Rev. 0
Freescale Semiconductor
33
$0018
ESCII Arbiter Control
Register
(SCIACTL)
Read:
AM1
ALOST
AM0
ACLK
AFIN
ARUN
AROVFL
ARD8
Write:
Reset:
0000
0
000
$0019
ESCI Arbiter Data Register
(SCIACTL)
Read:
ARD7
ARD6
ARD5
ARD4
ARD3
ARD2
ARD1
ARD0
Write:
Reset:
0000
0
000
$001A
Keyboard Status
and Control Register
(KBSCR)
Read:
0000
KEYF
0
IMASKK
MODEK
Write:
ACKK
Reset:
0000
0
000
$001B
Keyboard Interrupt Enable
Register (KBIER)
Read:
000
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
Write:
Reset:
0000
0
000
$001C
Timebase Control Register
(TBCR)
Read:
TBIF
TBR2
TBR1
TBR0
0
TBIE
TBON
R
Write:
TACK
Reset:
0000
0
000
$001D
IRQ Status and Control
Register (INTSCR)
Read:
0000
IRQF
0
IMASK
MODE
Write:
ACK
Reset:
0000
0
000
$001E
Configuration Register 2
(CONFIG2)
Read:
R
ESCI
BDSRC
EXT-
XTALEN
EXT-
SLOW
EXT-
CLKEN
TMB-
CLKSEL
OSCENIN-
STOP
SSB-
PUENB
Write:
Reset:
0000
0
001
$001F
Configuration Register 1
(CONFIG1)
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVI5OR3(1)
SSREC
STOP
COPD
Write:
Reset:
0000
0
000
1. The LVI5OR3 bit is cleared only by a power-on reset (POR).
$0020
Timer A Status and Control
Register (TASC)
Read:
TOF
TOIE
TSTOP
0
R
PS2
PS1
PS0
Write:
0
TRST
Reset:
0010
0
000
$0021
Timer A Counter Register
High (TACNTH)
Read:
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
Write:
Reset:
0000
0
000
$0022
Timer A Counter Register
Low (TACNTL)
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset:
0000
0
000
$0023
Timer A Counter Modulo
Register High (TAMODH)
Read:
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
Write:
Reset:
1111
1
111
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)