- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45238 > MC68HC711EA9MFS3 (FREESCALE SEMICONDUCTOR INC) 8-BIT, UVPROM, 3 MHz, MICROCONTROLLER, CQCC52 PDF資料下載
參數(shù)資料
| 型號： | MC68HC711EA9MFS3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 3 MHz, MICROCONTROLLER, CQCC52 |
| 封裝： | WINDOWED, CERAMIC, LCC-52 |
| 文件頁數(shù)： | 15/58頁 |
| 文件大小： | 583K |
| 代理商： | MC68HC711EA9MFS3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
MOTOROLA
MC68HC11EA9
22
MC68HC11EA9TS/D
5 Resets and Interrupts
All M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows:
RESET, or Power-On Reset
Clock Monitor Fail
COP Failure
The 18 interrupt vectors service 22 interrupt sources (3 non-maskable, 19 maskable). The 3 non-
maskable interrupt sources are as follows:
Illegal Opcode Trap
Software Interrupt
XIRQ Pin (X Interrupt)
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-
rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-
ing to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register (HPRIO). The HPRIO register can be written at any
time, provided bit I in the CCR is set.
Eighteen interrupt sources in the MC68HC(7)11EA9 MCUs are subject to masking by the global inter-
rupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external
interrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in the
M68HC11 have separate interrupt vectors; therefore, there is usually no need for software to poll control
registers to determine the cause of an interrupt.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system
is cleared by the automatic clearing mechanism invoked by a read of the SCI status register while RDRF
is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request
would be to read the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any
special instructions.
The computer operating properly (COP) watchdog and the clock monitor are both circuits that force a
reset sequence when a malfunctioning clock is encountered. The COP function forces a reset when a
timeout occurs. The timeout period is determined by programming CR[1:0] in OPTION register. The
clock monitor circuit forces a reset sequence whenever the clock is slow or absent. The CME bit in the
OPTION register enables the clock monitor circuit. To use STOP mode the clock monitor must be dis-
abled before the STOP instruction is executed or a reset sequence will occur.
Refer to the following table for a list of interrupt and reset vector assignments.
Table 7 Interrupt and Reset Vector Assignments
Vector Address
Interrupt Source
CCR Mask
Local Mask
Priority
(1 = High)
FFC0, C1 — FFD4, D5
Reserved
—
FFD6, D7
SCI Serial System
Bit I
18
SCI Receive Data Register Full
RIE
SCI Receiver Overrun
RIE
SCI Transmit Data Register Empty
TIE
SCI Transmit Complete
TCIE
SCI Idle Line Detect
ILIE
FFD8, D9
Reserved
—
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC711EA9MP3 | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP56 |
| MC68HC711EA9VFN3 | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC11EA9MFN3 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC711KS2VFN4 | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC711K4VFU4 | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC711K4CFN4 | 功能描述:IC MCU 24K OTP 4MHZ 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC711K4CFNE3 | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC711K4CFNE4 | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC711K4CFU4 | 功能描述:IC MCU 24K 4MHZ EEPROM 80-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC711KS2CPU4 | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。