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| 型號： | MC68HC711EA9MFS2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 2 MHz, MICROCONTROLLER, CQCC52 |
| 封裝： | WINDOWED, CERAMIC, LCC-52 |
| 文件頁數(shù)： | 4/58頁 |
| 文件大?。?/td> | 583K |
| 代理商： | MC68HC711EA9MFS2 |
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MOTOROLA
MC68HC11EA9
12
MC68HC11EA9TS/D
IRV(NE) — Internal Read Visibility(Not E)
IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on or
off. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
In single-chip modes this bit determines whether the E clock drives out from the chip.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
PSEL[3:0] — Priority Select Bits [3:0]
Refer to 5 Resets and Interrupts
4.6 RAM
In all modes RAM is enabled and present at locations $0000–$01FF. The RAM can be mapped to any
1-Kbyte boundary by writing an appropriate value to the INIT register. The INIT register must be written
during the first 64 cycles after reset in expanded and single-chip modes. If RAM and the register block
are placed at the same 1-Kbyte boundary, the first 64 bytes of RAM are inaccessible. This is due to an
on-chip hardware priority scheme which eliminates conflicts which could arise from multiple resources
sharing address locations. Figure 6 shows the location of the RAM array.
4.7 Bootstrap ROM
When operating in normal modes (SMOD = 0), the bootstrap ROM is disabled and removed from the
memory map. In bootstrap and special test modes, bootstrap ROM is present at $BF00–$BFFF. Boot-
strap ROM cannot be remapped to other locations. Figure 6 shows the location of the bootstrap ROM
array.
The bootstrap ROM contains a small program that allows program code to be downloaded into on-chip
RAM. When the MC68HC(7)11EA9 enters bootstrap mode, bootloader firmware residing in bootstrap
ROM begins the downloading procedure by initializing the SCI system and transmitting a break out the
SCI TxD pin. The SCI then waits for the first character to be received. After the first character is received
on the RxD pin of the SCI, bootloader firmware begins counting the number of bytes received. When
an idle time of four characters or the character for address $01FF is received, the bootloader program
terminates the download and control is passed to the loaded program at $0000. For a detailed descrip-
tion of the M68HC11 bootstrap mode, refer to application note
M68HC11 Bootstrap Mode (AN1060/D).
4.8 Memory Map and Register Block
The operating mode determines memory mapping and whether external addresses can be accessed.
Memory locations for on-chip resources are the same for both expanded and single-chip modes. Con-
trol bits in the CONFIG register allow ROM/EPROM and EEPROM to be disabled from the memory
map. The RAM is mapped to $0000 after reset. It can be placed at any 4 Kbyte boundary ($x000) by
writing an appropriate value to the INIT register. The 64-byte register block is mapped to $1000 after
reset and can also be placed at any 4 Kbyte boundary ($x000) by writing an appropriate value to the
INIT register. If RAM and registers are mapped to the same boundary, the first 64 bytes of RAM will be
inaccessible. Table 4 shows the arrangement of control registers and bits within the register block.
Table 3 IRVNE Control vs. Operating Mode
Operating
Mode
IRVNE Bit
Out of Reset
E Clock
Out of Reset
IRV Function
Out of Reset
IRVNE Bit
Affects Only
Single Chip
0
On
Off
E
Expanded
0
On
Off
IRV
Bootstrap
0
On
Off
E
Special Test
1
On
IRV
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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