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參數(shù)資料
| 型號： | MC68HC711E20MFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers |
| 中文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 184/268頁 |
| 文件大?。?/td> | 3696K |
| 代理商： | MC68HC711E20MFU2 |
Electrical Characteristics
Data Sheet
M68HC11E Family — Rev. 5
184
Electrical Characteristics
MOTOROLA
10.15 Expansion Bus Timing Characteristics
Num
Characteristic
(1)
Symbol
1.0 MHz
Min
2.0 MHz
Min
3.0 MHz
Min
Unit
Max
Max
Max
Frequency of operation (E-clock frequency)
f
o
dc
1.0
dc
2.0
dc
3.0
MHz
1
Cycle time
t
CYC
1000
—
500
—
333
—
ns
2
Pulse width, E low
(2)
, PW
EL
= 1/2 t
CYC
–23 ns
PW
EL
477
—
227
—
146
—
ns
3
Pulse width, E high
(2)
, PW
EH
= 1/2 t
CYC
–28 ns
PW
EH
472
—
222
—
141
—
ns
4a
E and AS rise time
t
r
t
f
—
20
—
20
—
20
ns
4b
E and AS fall time
—
20
—
20
—
15
ns
9
Address hold time
(2) (3)a
, t
AH
= 1/8 t
CYC
–29.5 ns
Non-multiplexed address valid time to E rise
t
AV
= PW
EL
–(t
ASD
+ 80 ns)
(2) (3)a
t
AH
95.5
—
33
—
26
—
ns
12
t
AV
281.5
—
94
—
54
—
ns
17
Read data setup time
t
DSR
t
DHR
30
—
30
—
30
—
ns
18
Read data hold time, max = t
MAD
0
145.5
0
83
0
51
ns
19
Write data delay time, t
DDW
= 1/8 t
CYC
+ 65.5 ns
(2) (3)a
t
DDW
—
190.5
—
128
71
ns
21
Write data hold time, t
DHW
= 1/8 t
CYC
–29.5 ns
(2) (3)a
Multiplexed address valid time to E rise
t
AVM
= PW
EL
–(t
ASD
+ 90 ns)
(2) (3)a
Multiplexed address valid time to AS fall
t
ASL
= PW
ASH
–70 ns
(2)
Multiplexed address hold time
t
AHL
= 1/8 t
CYC
–29.5 ns
(2) (3)b
t
DHW
95.5
—
33
—
26
—
ns
22
t
AVM
271.5
—
84
—
54
—
ns
24
t
ASL
151
—
26
—
13
—
ns
25
t
AHL
95.5
—
33
—
31
—
ns
26
Delay time, E to AS rise, t
ASD
= 1/8 t
CYC
–9.5 ns
(2) (3)a
t
ASD
115.5
—
53
—
31
—
ns
27
Pulse width, AS high, PW
ASH
= 1/4 t
CYC
–29 ns
(2)
PW
ASH
221
—
96
—
63
—
ns
28
Delay time, AS to E rise, t
ASED
= 1/8 t
CYC
–9.5 ns
(2) (3)b
t
ASED
115.5
—
53
—
31
—
ns
29
MPU address access time
(3)a
t
ACCA
= t
CYC
–(PW
EL
–t
AVM
) –t
DSR
–t
f
MPU access time, t
ACCE
= PW
EH
–t
DSR
Multiplexed address delay (Previous cycle MPU read)
t
MAD
= t
ASD
+ 30 ns
(2) (3)a
t
ACCA
744.5
—
307
—
196
—
ns
35
t
ACCE
—
442
—
192
111
ns
36
t
MAD
145.5
—
83
—
51
—
ns
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, all timing is shown with respect to 20% V
DD
and 70% V
DD
, unless
otherwise noted
2. Formula only for dc to 2 MHz
3. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 t
CYC
in the above formulas, where applicable:
(a) (1–dc)
×
1/4 t
CYC
(b) dc
×
1/4 t
CYC
Where:
dc is the decimal value of duty cycle percentage (high time)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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