參數(shù)資料
型號： MC68HC711D3CP3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 83/138頁
文件大小： 1047K
代理商： MC68HC711D3CP3
Interrupts
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
49
Bits 7, 6, and 2 — Not implemented
Always read 0.
IRQE — IRQ Edge/Level Sensitivity Select
This bit can be written only once during the first 64 E-clock cycles after reset in normal modes.
1 = IRQ is configured to respond only to falling edges.
0 = IRQ is configured for low-level wired-OR operation.
DLY — Stop Mode Exit Turnon Delay
This bit is set during reset and can be written only once during the first 64 E-clock cycles after reset in
normal modes. If an external clock source rather than a crystal is used, the stabilization delay can be
inhibited because the clock source is assumed to be stable.
1 = A stabilization delay of 4064 E-clock cycles is imposed before processing resumes after a stop
mode wakeup.
0 = No stabilization delay is imposed after story recovery.
CME — Clock Monitor Enable
1 = Clock monitor circuit is enabled.
0 = Clock monitor circuit is disabled.
CR1 and CR0 — COP Timer Rate Selects
The COP system is driven by a constant frequency of E
÷ 215. These two bits specify an additional
divide-by value to arrive at the COP timeout rate. These bits are cleared during reset and can be written
only once during the first 64 E-clock cycles after reset in normal modes. The value of these bits is:
4.3 Interrupts
Excluding reset-type interrupts, there are 17 hardware interrupts and one software interrupt that can be
generated from all the possible sources. These interrupts can be divided into two categories: maskable
and non-maskable. Fifteen of the interrupts can be masked using the I bit of the condition code register
(CCR). All the on-chip (hardware) interrupts are individually maskable by local control bits. The software
interrupt is non-maskable. The external input to the XIRQ pin is considered a non-maskable interrupt
because it cannot be masked by software once it is enabled. However, it is masked during reset and upon
receipt of an interrupt at the XIRQ pin. Illegal opcode is also a non-maskable interrupt.
Address:
$0039
Bit 7
654321
Bit 0
Read:
0
IRQE
DLY
CME
0
CR1
CR0
Write:
Reset:
00010000
Figure 4-2. System Configuration Options Register (OPTION)
CR1
CR0
E
÷ 215
Divided By
00
1
01
4
10
16
11
64
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