參數(shù)資料
型號： MC68HC705X4
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： HCMOS Microcontroller Unit
中文描述： HCMOS微控制器
文件頁數(shù)： 93/156頁
文件大小： 940K
代理商： MC68HC705X4
Motorola CAN
Interface to the MC68HC05X4 CPU
MC68HC05X4 Rev 1.0
Motorola CAN
25-mcan
Biphase mode
If the CAN modules are isolated from the bus lines by a transformer then
the bit stream has to be coded so that there is no resulting dc
component. There is a flip-flop within the MCAN that keeps the last
dominant configuration; its direct output goes to TX0 and its complement
to TX1. The flip-flop is toggled for each dominant bit; dominant bits are
thus sent alternately on TX0 and TX1; i.e. the first dominant bit is sent
on TX0, the second on TX1, the third on TX0 and so on. During
recessive bits, all output drivers are deactivated (i.e. high impedance).
Normal mode 1
In contrast to biphase mode the bit representation is time invariant and
not toggled.
Normal mode 2
For the TX0 pin this is the same as normal mode 1, however the data
stream to TX1 is replaced by the transmit clock. The rising edge of the
transmit clock marks the beginning of a bit time. The clock pulse will be
t
SCL
long.
Other output control bits
The other six bits in this register control the output driver configurations,
to determine the format of the output signal for a given data value (see
Figure 21
).
OCTP0/1 – These two bits control whether the P-type output control
transistors are enabled.
OCTN0/1 – These two bits control whether the N-type output control
transistors are enabled.
OCPOL0/1 – These two bits determine the driver output polarity for each
of the MCAN bus lines (TX0, TX1).
TP0/1 and TN0/1 – These are the resulting states of the output
transistors.
TD – This is the internal value of the data bit to be transferred across the
MCAN bus. (A zero corresponds to a dominant bit, a one to a recessive.)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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