參數(shù)資料
型號： MC68HC705RC16FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 81/120頁
文件大小： 547K
代理商： MC68HC705RC16FN
Core Timer
Core Timer Counter Register
MC68HC705RC16 — Rev. 3.0
General Release Specification
MOTOROLA
Core Timer
63
NON-DISCLOSURE
AGREEMENT
REQUIRED
8.4 Core Timer Counter Register
The timer counter register is a read-only register that contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked by the CPU clock (E/4) and can be used
for various functions, including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location, thereby simulating a 16-bit (or more) counter.
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released,
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer starts counting
up from zero and normal device operation begins. When RESET is
asserted any time during operation (other than POR and low-power
reset), the counter chain is cleared.
Address:
$09
Read:
D7
D6
D5
D4
D3
D2
D1
D0
Write:
Reset:
00000011
= Unimplemented
Figure 8-3. Core Timer Counter Register (CTCR)
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