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參數(shù)資料
| 型號(hào)： | MC68HC705PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 30/165頁(yè) |
| 文件大?。?/td> | 841K |
| 代理商： | MC68HC705PD6 |
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July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
P-DECODER
MOTOROLA
REV 1.1
12-9
12.3.7.1 Preamble Mode
After receiving the preamble pattern, it enters preamble mode and continues to
check the following 544 bits of data. If there is an SC inside the 544-bit time frame,
it will change to the receiving mode. Otherwise, it will change to the waiting mode.
The BS1 and BS3 signals hold at ‘1’ and the BS2 signal holds at ‘0’ for the whole
preamble mode duration.
12.3.7.2 Receiving Mode
The receiving mode starts with the frame 0 when the SC is detected in the
preamble mode. The battery saving signals, BS1, BS2 and BS3, will be changed
according to DS1-DS0, FA2-FA0, FB2-FB0, PLL1-PLL0 of the P-Decoder Control
Registers. The 32 bits of data in the self-frame number will be received and
compared to the six user addresses stored in ADR
A-ADRF. If the 1st 32 bits of
received data is not the same as one of the six addresses, the 2nd 32 bits of
received data in the same frame will also be compared. If it does not match, the
battery saving signals will hold at ‘0’. If the 1st or the 2nd codeword does match,
the DBF ag in the PDSR register is set. After the address information and 2
function bits are stored in the RAIR register, ADRF ag in PDSR register will be
set. The P-Decoder will keep BS1 = ‘1’, BS2 = ‘0’, BS3 = ‘1’ to receive the
message data. When 20 bits of message data are stored in the RMIR registers,
the MSGF ag is set. The receiving of message data will be terminated when it
meets other address codeword or the idle codeword and the DCF ag in PDSR
register will be set. In the receiving mode, it continues to detect the SC. If it does
not detect the SC, the SCF ag in PDSR will be cleared. If the SC is absent
consecutively for 2 times, the operating mode will be changed to the waiting
mode. The SCF ag in PDSR register will be set when the SC is detected and
cleared when the SC is not detected. The ERRF ag in PDSR shows the validity
of the 20-bit message data. In most situation, if ERRF = ‘0’, there is 2 or less than
2 bits error and the data in the RMIR register is valid. If ERRF = ‘1’, there is more
than 2 bits error and the data in the RMIR register is invalid. Message codewords
following this error codeword will be ignored. Figure 12-6 and Figure 12-7 show
the timing of signals in the receiving mode.
12.3.8 Frame State Generator
In each batch, there are one SC and sixteen codewords. State 16 is assigned to
SC, state 0 is assigned to the 1st codeword and state 15 is assigned to the 16th
codeword sequentially. It provides the information to generate the battery saving
signals.
12.3.9 Preamble and Synchronization Codeword Detector
It is used to detect the preamble pattern and synchronization codeword.
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