參數(shù)資料
型號(hào): MC68HC705P9DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 31/160頁
文件大?。?/td> 2208K
代理商: MC68HC705P9DW
Serial Input/Output Port (SIOP)
Technical Data
MC68HC705P9 — Rev. 4.0
126
Serial Input/Output Port (SIOP)
MOTOROLA
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
1 = SIOP enabled
0 = SIOP disabled
MSTR — Master Mode Select
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can
be set at any time regardless of the state of SPE. Reset clears MSTR.
1 = Master mode selected
0 = Slave mode selected
10.7.2 SIOP Status Register
The read-only SIOP status register (SSR) contains two bits. One bit
indicates that a SIOP transfer is complete, and the other indicates that
an invalid access of the SIOP data register occurred while a transfer was
in progress.
SPIF — Serial Peripheral Interface Flag
This clearable, read-only bit is set automatically on the eighth rising
edge on the PB7/SCK pin and indicates that a data transmission took
place. SPIF does not inhibit further transmissions. Clear SPIF by
reading the SIOP status register while SPIF is set and then reading or
writing the SIOP data register. Reset clears SPIF.
1 = Transmission complete
0 = Transmission not complete
DCOL — Data Collision Flag
$000B
Bit 7
6
54321
Bit 0
Read:
SPIF
DCOL
000000
Write:
Reset:
00
000000
Figure 10-7. SIOP Status Register (SSR)
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For More Information On This Product,
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相關(guān)PDF資料
PDF描述
MC68HC705P9MS 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
MC68HC705P9CDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P9VS 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
MC68HC705P9S 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
MC68HC705P9VDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
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