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參數(shù)資料
| 型號： | MC68HC705P6ACP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 49/130頁 |
| 文件大?。?/td> | 1541K |
| 代理商： | MC68HC705P6ACP |
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Interrupts
Interrupt Types
MC68HC705P6A
—
Rev. 2.0
Advance Information
MOTOROLA
Interrupts
49
$1FFA and $1FFB. If the port A interrupts are enabled by the MOR, they
generate external interrupts identically to the IRQ/V
PP
pin.
NOTE:
The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the
IRQ service routine.
Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.
5.3.3.2 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in
Section 8. Capture/Compare Timer
. The input capture interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the input capture
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $1FF8 and $1FF9.
5.3.3.3 Output Compare Interrupt
The output compare interrupt is generated by a 16-bit timer as described
in
Section 8. Capture/Compare Timer
.
The output compare interrupt
flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the output
compare interrupt to be enabled. The interrupt service routine address is
specified by the contents of memory locations $1FF8 and $1FF9.
5.3.3.4 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described
in
Section 8. Capture/Compare Timer
. The timer overflow interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the timer overflow
interrupt to be enabled. This internal interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF8 and $1FF9.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC705P6ADW | 制造商:Rochester Electronics LLC 功能描述:MCU, 176 BYTES RAM, A/D - Bulk |
| MC68HC705P6AMDW | 功能描述:IC MCU 4.6K OTP 2.1MHZ 28-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC705P6AMP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HC705P6CDW | 制造商:Motorola Inc 功能描述: |
| MC68HC705P6CP | 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
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