參數(shù)資料
型號： MC68HC705J1ACPE
廠商： Freescale Semiconductor
文件頁數(shù)： 113/162頁
文件大?。?/td> 0K
描述： IC MCU 4MHZ 1.2K OTP 20-DIP
標準包裝： 18
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 4MHz
外圍設備： POR，WDT
輸入/輸出數(shù)： 14
程序存儲器容量： 1.2KB（1.2K x 8）
程序存儲器類型： OTP
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-DIP（0.300"，7.62mm）
包裝： 管件
Technical Data
MC68HC705J1A — Rev. 4.0
Central Processor Unit (CPU)
Central Processor Unit (CPU)
The k value is typically in the index register, and the address of the
beginning of the table is in the byte following the opcode.
3.6.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Freescale assembler
determines the shortest form of indexed addressing.
3.6.1.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to
calculate the offset because the assembler determines the proper offset
and verifies that it is within the span of the branch.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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