參數(shù)資料
型號(hào)： MC68HC705C9AVFNE
廠商： Freescale Semiconductor
文件頁數(shù)： 27/118頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 352 BYTES RAM 44-PLC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 24
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 352 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
General Description
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
16
Freescale Semiconductor
The port D data direction register ($0007) is disabled and the seven port D pins become input only.
SPI output signals (MOSI, MISO, and SCK) do not require the data direction register control for
output capability.
The port D wire-OR mode control bit (bit 5 of SPCR $000A) is disabled, preventing open-drain
configuration of port D.
The RESET pin becomes input only.
1.4 Mask Options
The following two mask option registers are used to select features controlled by mask changes on the
MC68HC05C9A and the MC68HC05C12A:
Port B mask option register (PBMOR)
C12 mask option register (C12MOR)
The mask option registers are EPROM locations which must be programmed prior to operation of the
microcontroller.
1.4.1 Port B Mask Option Register (PBMOR)
The PBMOR register, shown in Figure 1-2, contains eight programmable bits which determine whether
each port B bit (when in input mode) has the pullup and interrupt enabled. The port B interrupts share the
vector and edge/edge-level sensitivity with the IRQ pin. For more details, (see 4.3 External Interrupt (IRQ
PBPU7–PBPU0 — Port B Pullup/Interrupt Enable Bits
1 = Pullup and CPU interrupt enabled
0 = Pullup and CPU interrupt disabled
NOTE
The current capability of the port B pullup devices is equivalent to the
MC68HC05C9A, which is less than the MC68HC05C12A.
1.4.2 C12 Mask Option Register (C12MOR)
The C12MOR register, shown in Figure 1-3, controls the following options:
Select between MC68HC05C9A/C12A configuration
Enable/disable stop mode (C12A mode only)
Enable/disable COP (C12A mode only)
Edge-triggered only or edge- and level-triggered external interrupt pin (IRQ pin) (C12A mode only).
$3FF0
Bit 7
654321
Bit 0
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
Figure 1-2. Port B Mask Option Register
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