參數(shù)資料
型號: MC68HC705C9AFNE
廠商: Freescale Semiconductor
文件頁數(shù): 94/118頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 44-PLCC
標準包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SCI,SPI
外圍設備: POR,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: OTP
RAM 容量: 352 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
SPI Registers
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
77
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to
the SPCR. Control bits SPE and MSTR may be restored by user software to their original state during
this clearing sequence or after the MODF bit has been cleared. When configured as an
MC68HC05C9A, it is also necessary to restore DDRD after a mode fault.
Bits 5 and 3–0 — Not Implemented
These bits always read 0.
10.5.3 Serial Peripheral Data I/O Register
The serial peripheral data I/O register (SPDR), shown in Figure 10-6, is used to transmit and receive data
on the serial bus. Only a write to this register will initiate transmission/reception of another byte and this
will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is
set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF
must be cleared by the time a second transfer of the data from the shift register to the read buffer is
initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places data directly into the shift
register for transmission.
$000C
Bit 7
654321
Bit 0
Read:
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Write:
Reset:
Unaffected by reset
Figure 10-6. PI Data Register (SPDR)
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