參數(shù)資料
型號(hào)： MC68HC705C9A
廠商： Motorola, Inc.
英文描述： Microcontrollers
中文描述： 微控制器
文件頁數(shù)： 99/160頁
文件大?。?/td> 2076K
代理商： MC68HC705C9A
Serial Communications Interface (SCI)
SCI I/O Registers
MC68HC705C9A — Rev. 4.0
Advance Information
MOTOROLA
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
99
TDRE — Transmit Data Register Empty Flag
This clearable, read-only flag is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to
avoid an instant interrupt request when turning the transmitter on.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Flag
This clearable, read-only flag is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TDRE
generates an interrupt request if the TCIE bit in SCCR2 is also set.
Clear the TC bit by reading the SCSR with TC set, and then writing to
the SCDR. Reset sets the TC bit. Software must initialize the TC bit
to logic 0 to avoid an instant interrupt request when turning the
transmitter on.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Flag
This clearable, read-only flag is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in the SCCR2 is also set. Clear the
RDRF bit by reading the SCSR with RDRF set and then reading the
SCDR.
1 = Received data available in SCDR
0 = Received data not available in SCDR
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
Write:
Reset:
1
1
0
0
0
0
0
—
= Unimplemented
Figure 9-11. SCI Status Register (SCSR)
F
Freescale Semiconductor, Inc.
n
.
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