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Technical Data
MC68HC705C8A — Rev. 3
70
Low-Power Modes
MOTOROLA
Low-Power Modes
Figure 6-1. Stop/Wait Mode Function Flowchart
During stop mode, the I bit in the condition code register (CCR) is
cleared to enable external interrupts. All other registers and memory
remain unaltered. All input/output (I/O) lines remain unchanged. The
processor can be brought out of stop mode only by an external interrupt
or reset.
NO
YES
NO
YES
NO
YES
STOP
RESET
EXTERNAL
INTERRUPT
(IRQ)
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
1. FETCH RESET VECTOR
2. SERVICE INTERRUPT:
a. STACK
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
WAIT
OSCILLATOR ACTIVE
TIMER, SCI, AND SPI
CLOCKS ACTIVE
CPU CLOCKS STOPPED
RESET
EXTERNAL
INTERRUPT
(IRQ)
INTERNAL TIMER
INTERRUPT
INTERNAL SCI
INTERRUPT
INTERNAL SPI
INTERRUPT
RESTART CPU CLOCK
1. FETCH RESET VECTOR
2. SERVICE INTERRUPT:
a. STACK
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
CLEAR I BIT
OR