
MC68HC05B6
Rev. 4.1
Freescale
1-3
INTRODUCTION
1
1.2
Mask options for the MC68HC05B6
The MC68HC05B6 has three mask options that are programmed during manufacture and must
be specified on the order form.
Power-on-reset delay (tPORL) = 16 or 4064 cycles
Automatic watchdog enable/disable following a power-on or external reset
Watchdog enable/disable during WAIT mode
Warning: It is recommended that an external clock is always used if tPORL is set to 16 cycles. This
will prevent any problems arising with oscillator stability when the device is put into
STOP mode.
Figure 1-1 MC68HC05B6 block diagram
Por
tA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port
B
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port
C
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
16-bit
programmable
timer
Port
D
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
Oscillator
176 bytes
RAM
COP watchdog
RESET
IRQ
VDD
VSS
OSC1
OSC2
M68HC05
CPU
SCI
A/D converter
PLM
TCAP1
TCAP2
TCMP1
TCMP2
VRH
VRL
RDI
SCLK
TDO
VPP1
256 bytes
EEPROM
Charge pump
÷ 2 / ÷ 32
PLMA D/A
PLMB D/A
8-bit
432 bytes
User ROM
5950 bytes
self check ROM
(including 14 bytes
User vectors)