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參數(shù)資料
| 型號： | MC68HC681FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 54/88頁 |
| 文件大?。?/td> | 461K |
| 代理商： | MC68HC681FN |
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Electrical Specifications
5-4
MC68HC681 USER’S MANUAL
MOTOROLA
5
5.5.2 RESET Timing
Figure 5-2. RESET Timing
5.5.3 Read and Write Bus Cycle Timing
CHARACTERISTIC
SYMBOL
MIN
MAX
UNIT
RESET Pulse Width*
tRES
1.0
—
s
NOTE: * The MC68HC681 does not require a clock for correct reset
CHARACTERISTIC
SYMBOL
MIN
MAX
UNIT
CS Setup Time to X1 High 1
tCSC
90
—
ns
RS1-RS4 Setup Time to CS Asserted
tRSS
10
—
ns
R/W Setup Time to CS Asserted
tRWS
10
—
ns
CS Pulse Width Asserted 2
tCSWL
205
—
ns
Data Valid from CS Asserted
tDD
—
175
ns
DTACK Asserted from X1 High
tDCR
—
125
ns
CS Negated from DTACK Asserted 2
tCSD
0—
ns
RS1-RS4 Hold Time from CS Negated
tRSH
0—
ns
R/W Hold Time from CS Negated
tRWH
0—
ns
Data Hold Time from CS Negated
tDH
0—
ns
Data Bus Floating from CS Negated
tDF
—
100
ns
DTACK Negated from CS Negated
tDAH
—
ns
DTACK Hi-Z from CS Negated
tDAT
—
125
ns
CS Pulse Width Negated
tCSWH
90
—
ns
Data Setup Time to CS Negated 3
tDSCS
100
—
ns
DTACK Asserted from X1 High
tDCW
—
125
ns
Data Hold Time from CS Negated
tDH
0—
ns
NOTES:
1.
This specication is only to ensure DTACK is asserted with respect to the rising edge of X1 as shown in Figure 5-3 and Figure 5-
4, not to guarantee operation of the part. If the setup time is violated, DTACKmay be asserted as shown, or may be asserted one
clock cycle later.
2.
This specication is only to ensure that DTACK will be asserted. If CS is negated before DTACK is asserted, DTACK may not be
asserted.
3.
During write cycles, the MC68681 latched data on either the assertion edge of DTACKor the negation edge of CS, whichever
occurred rst. This is not true in the MC68HC681: the MC68HC681 always latches write data on the negation edge of CS.
RESET
tRES
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