
M68HC16 Z SERIES
REGISTER SUMMARY
USER’S MANUAL
D-63
RDRF — Receive Data Register Full
0 = Receive data register is empty or contains previously read data.
1 = Receive data register contains new data.
RAF — Receiver Active
0 = SCI receiver is idle.
1 = SCI receiver is busy.
IDLE — Idle-Line Detected
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
OR — Overrun Error
0 = Receive data register is empty and can accept data from the receive serial
shifter.
1 = Receive data register is full and cannot accept data from the receive serial
shifter. Any data in the shifter is lost and RDRF remains set.
NF — Noise Error
0 = No noise detected in the received data.
1 = Noise detected in the received data.
FE — Framing Error
0 = No framing error detected in the received data.
1 = Framing error or break detected in the received data.
PF — Parity Error
0 = No parity error detected in the received data.
1 = Parity error detected in the received data.
D.7.12 SCI Data Register
SCDR consists of two data registers located at the same address. The receive data
terface. Data comes into the receive serial shifter and is transferred to RDR. The trans-
mit data register (TDR) is a write-only register that contains data to be transmitted.
Data is first written to TDR, then transferred to the transmit serial shifter, where addi-
tional format bits are added before transmission. R[7:0]/T[7:0] contain either the first
eight data bits received when SCDR is read, or the first eight data bits to be transmitted
when SCDR is written. R8/T8 are used when the SCI is configured for nine-bit opera-
tion. When the SCI is configured for 8-bit operation, R8/T8 have no meaning or effect.
SCDRA — SCIA Data Register
$YFFC1E
SCDRB — SCIB Data Register
$YFFC2E
15
9
8
7
6
5
4
3
2
1
0
NOT USED
R8/T8
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
RESET:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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