
Memory Expansion and Chip Selects
Chip Selects
M68HC11K Family
Technical Data
MOTOROLA
Memory Expansion and Chip Selects
239
Table 11-4. Chip Select Control Parameter Summary
CSIO
Enable
IOEN in CSCTL
1 = enabled, 0 = disabled(1)
Valid
IOCSA in CSCTL
1 = address valid, 0(1) = E high
Polarity
IOPL in CSCTL
1 = active high, 0 = active low(1)
Size
IOSZ in CSCTL
1 = 4 K ($1000–$1FFF)
0 = 8 K ($0000–$1FFF)(1)
Start address
Fixed (see size)
Stretch
IO1S[A:B] in CSCSTR
0(1), 1, 2, or 3 E clocks
CSPROG
Enable
PCSEN in CSCTL
1 = enabled(1), 0 = disabled
Valid
Fixed (address valid)
Polarity
Fixed (active low)
Size
PCSZ[A:B] in CSCTL
0:0 = 64 K ($0000–$FFFF)(1)
0:1 = 32 K ($8000–$FFFF)
1:0 = 16 K ($C000–$FFFF)
1:1 = 8 K ($E000–$FFFF)
Start address
Fixed (see size)
Stretch
PCS[A:B] in CSCSTR
0(1), 1, 2, or 3 E clocks
Priority
GCSPR in CSCTL
1 = CSGPx above CSPROG
0(1) = CSPROG above CSGPx
CSGP1,
Enable
Set size to 0K to disable
CSGP2
Valid
G1AV in GPCS1C
G2AV in GPCS2C
1 = address valid, 0 = E high(1)
Polarity
G1POL in GPS1C
G2POL in GPS2C
1 = active high, 0 = active low(1)
Size
G1SZ[A:D] in GPCS1C
G1SZ[A:D] in GPCS2C
2 K to 512 K in nine steps
0K = disabled(1) can also follow memory
expansion window 1 or window 2
Start address
GPCS1A
GPCS2A
Stretch
CSCSTR
0(1), 1, 2, or 3 E clocks
Other
G1DG2 in GPCS1C
Allows CSGP1 and CSGP2 to be logically ORed
and driven out the CSGP2 pin
G1DPC in GPCS1C
Allows CSGP1 and CSPROG to be logically
ORed and driven out the CSPROG pin
G2DPC in GPCS2C
Allows CSGP2 and CSPROG to be logically
ORed and driven out the CSPROG pin.
MXGS2 in MMSIZ
Allows CSGP2 to follow either 64 K CPU
addresses or 512K expansion addresses
MXGS1 in MMSIZ
Allows CSGP1 to follow either 64 K CPU
addresses or 512K expansion addresses
1. Configuration at reset
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Freescale Semiconductor, Inc.
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