參數(shù)資料
型號： MC68HC11F1CFN3R2
廠商： Freescale Semiconductor
文件頁數(shù)： 33/158頁
文件大?。?/td> 0K
描述： IC MCU 512 EEPROM 3MHZ 68-PLCC
標(biāo)準(zhǔn)包裝： 250
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 3MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 帶卷 (TR)
其它名稱： MC68HC11F1CFN3TR
ANALOG-TO-DIGITAL CONVERTER
MC68HC11F1
10-4
TECHNICAL DATA
indicates when valid data is present in the result registers. The result registers are writ-
ten during a portion of the system clock cycle when reads do not occur, so there is no
conflict.
10.1.5 A/D Converter Clocks
The CSEL bit in the OPTION register selects whether the A/D converter uses the sys-
tem E clock or an internal RC oscillator for synchronization. When the A/D system is
operating with the MCU E clock, all switching and comparator functions are synchro-
nized to the MCU clocks. This allows the comparator results to be sampled at relatively
quiet clock times to minimize noise errors.
When E-clock frequency is below 750 kHz, charge leakage in the capacitor array can
cause errors, and the internal oscillator should be used. The RC clock is asynchronous
to the MCU internal E clock. Therefore, when the RC clock is used, additional errors
can occur because the comparator is sensitive to the additional system clock noise.
10.1.6 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A
conversion sequence can repeat continuously or stop after one iteration. The conver-
sion complete flag (CCF) is set after the fourth conversion in a sequence to show the
availability of data in the result registers. Figure 10-3 shows the timing of a typical se-
quence. Synchronization is referenced to the system E clock.
Figure 10-3 A/D Conversion Sequence
MSB
4
CYCLES
E CLOCK
WRITE
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
END
12 E CYCLES
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE
2
CYC
CONVERT FOURTH
CHANNEL
AND UPDATE ADDR4
CONVERT THIRD
CHANNEL
AND UPDATE ADDR3
CONVERT SECOND
CHANNEL
AND UPDATE ADDR2
CONVERT FIRST
CHANNEL
AND UPDATE ADDR1
SET
REPEAT
E
CYCLES
128
96
64
32
0
TO
ADCTL
SEQUENCE
IF
SCAN = 1
CCF
FLAG
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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