參數(shù)資料
型號: MC68HC11F1CFN3
廠商: Freescale Semiconductor
文件頁數(shù): 117/158頁
文件大?。?/td> 0K
描述: IC MCU 512 EEPROM 3MHZ 68-PLCC
標(biāo)準(zhǔn)包裝: 18
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 3MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 30
程序存儲器類型: ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
OPERATING MODES AND ON-CHIP MEMORY
TECHNICAL DATA
4-23
Table 4-12 Chip Select Control Parameter Summary
CSIO1
Enable
IO1EN in CSCTL —
1 = On, off at reset (0)
Valid
IO1AV in CSGSIZ —
1 = Address valid, 0 = E valid
Polarity
IO1PL in CSCTL —
1 = Active high, 0 = Active low
Size
Fixed —
($x060–$x7FF)
Start Address
$x060 —
“x” is determined by REG[3:0] in INIT
Stretch
IO1SA–IO1SB in CSSTRH — 0, 1, 2, or 3 E clocks
CSIO2
Enable
IO2EN in CSCTL —
1 = On, off at reset (0)
Valid
IO2AV in CSGSIZ —
1 = Address valid, 0 = E valid
Polarity
IO2PL in CSCTL —
1 = Active high, 0 = Active low
Size
Fixed —
($x800–$xFFF)
Start Address
$x800 —
“x” is determined by REG[3:0] in INIT
Stretch
IO2SA–IO2SB in CSSTRH — 0, 1, 2, or 3 E clocks
CSPROG
Enable
PCSEN in CSCTL —
1 = On, on after reset in expanded modes
off after reset in single-chip modes
Valid
Fixed (Address valid)
Polarity
Fixed (Active low)
Size
PSIZA–PSIZB —
0:0 = 64K ($0000–$FFFF)
in CSCTL
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
Start Address
Fixed (determined by size)
Stretch
PSTHA–PSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
1 cycle after reset in expanded mode
no delay after reset in all other modes
Priority
GCSPR in CSCTL —
1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
CSGEN
Enable
Set size to 0K to disable —
1 = CSGEN above CSPROG
0 = CSPROG above CSGEN
Valid
GAVLD in CSGSIZ —
Address valid or E valid
Polarity
GNPOL in CSGSIZ —
Active high or low
Size
GSIZA–GSIZC in CSGSIZ — Refer to Table 4–12
Start Address
GA[15:10] in CSGADR
Stretch
GSTHA–GSTHB in CSSTRH — 0, 1, 2, or 3 E clocks
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