
Resets and Interrupts
Data Sheet
M68HC11E Family — Rev. 5
102
Resets and Interrupts
MOTOROLA
Figure 5-5. Processing Flow Out of Reset (Sheet 1 of 2)
2A
BIT X IN
CCR = 1
Y
N
XIRQ
PIN LOW
Y
N
BEGIN INSTRUCTION
SEQUENCE
1A
STACK CPU
REGISTERS
SET BITS
I
AND
X
FETCH VECTOR
$FFF4, $FFF5
SET BITS
S
,
I
, AND
X
RESET MCU
HARDWARE
POWER-ON RESET
(POR)
EXTERNAL RESET
CLOCK MONITOR FAIL
(WITH CME = 1)
COP WATCHDOG
TIMEOUT
(WITH NOCOP = 0)
DELAY 4064 E CYCLES
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFE, $FFFF
(VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFC, $FFFD
(VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFA, $FFFB
(VECTOR FETCH)
HIGHEST
PRIORITY
LOWEST
PRIORITY
F
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