Resets and Interrupts
Interrupts
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Resets and Interrupts
103
Figure 5-5. Processing Flow Out of Reset (Sheet 2 of 2)
BIT I IN
CCR = 1
2A
Y
N
ANY I-BIT
INTERRUPT
PENDING
Y
N
FETCH OPCODE
ILLEGAL
OPCODE
Y
N
WAI
Y
N
INSTRUCTION
SWI
INSTRUCTION
Y
N
RTI
INSTRUCTION
Y
N
EXECUTE THIS
INSTRUCTION
STACK CPU
REGISTERS
ANY
N
Y
INTERRUPT
PENDING
SET BIT
I
IN CCR
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
SEE FIGURE 5–2
STACK CPU
REGISTERS
SET BIT
I
IN CCR
FETCH VECTOR
$FFF8, $FFF9
STACK CPU
REGISTERS
SET BIT
I
IN CCR
FETCH VECTOR
$FFF6, $FFF7
RESTORE CPU
REGISTERS
FROM STACK
1A
STACK CPU
REGISTERS
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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