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參數(shù)資料
| 型號(hào)： | MC68HC11E9BCFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | POT 20K OHM 1/2 SQ CERM SL MT |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 148/268頁(yè) |
| 文件大?。?/td> | 3696K |
| 代理商： | MC68HC11E9BCFU2 |
Timing System
Data Sheet
M68HC11E Family — Rev. 5
148
Timing System
MOTOROLA
9.3.3 Timer Input Capture 4/Output Compare 5 Register
Use TI4/O5 as either an input capture register or an output compare register,
depending on the function chosen for the PA3 pin. To enable it as an input capture
pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic
level 1. To use it as an output compare register, set the I4/O5 bit to a logic level 0.
Refer to
9.7 Pulse Accumulator
.
9.4 Output Compare
Use the output compare (OC) function to program an action to occur at a specific
time — when the 16-bit counter reaches a specified value. For each of the five
output compare functions, there is a separate 16-bit compare register and a
dedicated 16-bit comparator. The value in the compare register is compared to the
value of the free-running counter on every bus cycle. When the compare register
matches the counter value, an output compare status flag is set. The flag can be
used to initiate the automatic actions for that output compare function.
To produce a pulse of a specific duration, write a value to the output compare
register that represents the time the leading edge of the pulse is to occur. The
output compare circuit is configured to set the appropriate output either high or low,
depending on the polarity of the pulse being produced. After a match occurs, the
output compare register is reprogrammed to change the output pin back to its
inactive level at the next match. A value representing the width of the pulse is
added to the original value, and then written to the output compare register.
Because the pin state changes occur at specific values of the free-running counter,
the pulse width can be controlled accurately at the resolution of the free-running
counter, independent of software latencies. To generate an output signal of a
specific frequency and duty cycle, repeat this pulse-generating procedure.
The five 16-bit read/write output compare registers are: TOC1, TOC2, TOC3, and
TOC4, and the TI4/O5. TI4/O5 functions under software control as either IC4 or
OC5. Each of the OC registers is set to $FFFF on reset. A value written to an OC
Register name: Timer Input Capture 4/Output Compare 5 (High)
Address: $101E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
1
1
1
1
1
1
1
1
Register name: Timer Input Capture 4/Output Compare 5 (Low)
Address: $101F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
1
1
1
1
1
1
1
1
Figure 9-7. Timer Input Capture 4/Output
Compare 5 Register Pair (TI4/O5)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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