
Technical Data
MC68HC11E Family — Rev. 4
240
Electrical Characteristics
MOTOROLA
Electrical Characteristics
11.14 Analog-to-Digital Converter Characteristics
Characteristic(1)
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, 750 kHz ≤ E ≤ 3.0 MHz, unless otherwise noted
Parameter(2)
2. Source impedances greater than 10 k
affect accuracy adversely because of input leakage.
Min
Absolute
2.0 MHz 3.0 MHz
Unit
Max
Resolution
Number of bits resolved by A/D converter
—
8
——
Bits
Non-linearity
Maximum deviation from the ideal A/D
transfer characteristics
——
±1/2
±1LSB
Zero error
Difference between the output of an ideal and
an actual for 0 input voltage
——
±1/2
±1LSB
Full scale error
Difference between the output of an ideal and
an actual A/D for full-scale input voltage
——
±1/2
±1LSB
Total unadjusted
error
Maximum sum of non-linearity, zero error, and
full-scale error
——
±1/2
LSB
Quantization
error
Uncertainty because of converter resolution
——
±1/2
LSB
Absolute
accuracy
Difference between the actual input voltage
and the full-scale weighted equivalent of the
binary output code, all error sources
included
——
±1
±2LSB
Conversion
range
Analog input voltage range
VRL
—
VRH
V
VRH
Maximum analog reference voltage(3)
3. Performance verified down to 2.5 V
V
R, but accuracy is tested and guaranteed at VR = 5 V ±10%.
VRL
—
VDD +0.1 VDD +0.1 V
VRL
Minimum analog reference voltage(2)
VSS –0.1
—
VRH
V
R
Minimum difference between VRH and VRL
(2)
3
——
—
V
Conversion
time
Total time to perform a single A/D conversion:
E clock
Internal RC oscillator
—
32
—
tcyc +32
—
tcyc +32
tcyc
s
Monotonicity
Conversion result never decreases with an
increase in input voltage; has no missing
codes
—
Guaranteed
——
—
Zero input
reading
Conversion result when VIn = VRL
00
——
—
Hex
Full scale
reading
Conversion result when VIn = VRH
——
FF
Hex
Sample
acquisition
time
Analog input acquisition sampling time:
E clock
Internal RC oscillator
—
12
—
12
—
12
tcyc
s
Sample/hold
capacitance
Input capacitance during sample
PE[7:0]
—
20 typical
——
pF
Input leakage
Input leakage on A/D pins
PE[7:0]
VRL, VRH
—
400
1.0
400
1.0
nA
A