
Technical Data
MC68HC11E Family — Rev. 4
202
Timing System
MOTOROLA
Timing System
9.6.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The
remaining bits control the pulse accumulator and IC4/OC5 functions.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
These two bits determine the rate at which the RTI system requests
interrupts. The RTI system is driven by an E divided by 213 rate clock
that is compensated so it is independent of the timer prescaler. These
two control bits select an additional division factor. Refer to Table 9-5.
Address:
$1026
Bit 7
6
54321
Bit 0
Read:
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Write:
Reset:
00
000000
Figure 9-23. Pulse Accumulator Control Register (PACTL)