
Technical Data
MC68HC11E Family — Rev. 4
188
Timing System
MOTOROLA
Timing System
high-order byte of an output compare register pair inhibits the output
compare function for one bus cycle. This inhibition prevents
inappropriate subsequent comparisons. Coherency requires a complete
16-bit read or write. However, if coherency is not needed, byte accesses
can be used.
For output compare functions, write a comparison value to output
compare registers TOC1–TOC4 and TI4/O5. When TCNT value
matches the comparison value, specified pin actions occur.
Register name: Timer Output Compare 1 Register (High)
Address: $1016
Bit 7
6
54321
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
1
111111
Register name: Timer Output Compare 1 Register (Low)
Address: $1017
Bit 7
6
54321
Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
1
111111
Figure 9-8. Timer Output Compare 1 Register Pair (TOC1)
Register name: Timer Output Compare 2 Register (High)
Address: $1018
Bit 7
6
54321
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
1
111111
Register name: Timer Output Compare 2 Register (Low)
Address: $1019
Bit 7
6
54321
Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
1
111111
Figure 9-9. Timer Output Compare 2 Register Pair (TOC2)