Electrical Characteristics
Serial Peripheral Interface Timing Characteristics
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Electrical Characteristics
187
10.17 Serial Peripheral Interface Timing Characteristics
Num
Characteristic
(1)
Symbol
E9
E20
Unit
Min
Max
Min
Max
Frequency of operation
E clock
f
o
dc
3.0
dc
3.0
MHz
E-clock period
t
CYC
333
—
333
—
ns
Operating frequency
Master
Slave
f
op(m)
f
op(s)
f
o
/32
dc
f
o
/2
f
o
f
o
/128
dc
f
o
/2
f
o
MHz
1
Cycle time
Master
Slave
t
CYC(m)
t
CYC(s)
2
1
32
—
2
1
128
—
t
CYC
2
Enable lead time
(2)
Slave
t
lead(s)
1
—
1
—
t
CYC
3
Enable lag time
(2)
Slave
t
lag(s)
1
—
1
—
t
CYC
4
Clock (SCK) high time
Master
Slave
t
w(SCKH)m
t
w(SCKH)s
t
CYC
–25
1/2 t
CYC
–25
16 t
CYC
—
t
CYC
–25
1/2 t
CYC
–25
64 t
CYC
—
ns
5
Clock (SCK) low time
Master
Slave
t
w(SCKL)m
t
w(SCKL)s
t
CYC
–25
1/2 t
CYC
–25
16 t
CYC
—
t
CYC
–25
1/2 t
CYC
–25
64 t
CYC
—
ns
6
Data setup time (inputs)
Master
Slave
t
su(m)
t
su(s)
30
30
—
—
30
30
—
—
ns
7
Data hold time (inputs)
Master
Slave
t
h(m)
t
h(s)
30
30
—
—
30
30
—
—
ns
8
Slave access time
CPHA = 0
CPHA = 1
Disable time (hold time
to high-impedance state)
Slave
t
a
0
0
40
40
0
0
40
40
ns
9
t
dis
—
50
—
50
ns
10
Data valid
(3)
(after enable edge)
Data hold time (outputs)
(after enable edge)
t
v
—
50
—
50
ns
11
t
ho
0
—
0
—
ns
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, all timing is shown with respect to 20% V
DD
and 70% V
DD
, unless
otherwise noted
2. Time to data active from high-impedance state
3. Assumes 200 pF load on SCK, MOSI, and MISO pins
F
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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.
