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參數(shù)資料
| 型號： | MC68HC11D3CP1 |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 62/124頁 |
| 文件大?。?/td> | 6875K |
| 代理商： | MC68HC11D3CP1 |
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OPERATING MODES AND ON-CHIP MEMORY
4-8
TECHNICAL DATA
PSEL[3:0] — Priority Select Bits
Refer to SECTION 5 RESETS AND INTERRUPTS.
4.2.2 System Initialization
Registers and bits that control initialization and the basic configuration of the MCU are
protected against writes except under special circumstances. The protection mecha-
nism, overridden in special operating modes, permits writing these bits only within the
first 64 bus cycles after any reset, and then only once after each reset. If the MCU is
going to be changed to a normal mode after being reset in a special mode, write to the
protected registers before writing the SMOD control bit to zero.
4.2.2.1 CONFIG Register
The CONFIG register consists of static latches that control the startup configuration of
the MCU. CONFIG is writable only once in expanded and single-chip modes (SMOD
= 0). In these modes, the COP watchdog timer is enabled out of reset.
Bits [7:3] and 0 — Not implemented
Always read zero
NOCOP — COP System Disable
This bit is cleared out of reset in normal modes (COP enabled). Refer to SECTION 5
0 = COP system enabled
1 = COP system disabled
ROMON — ROM Enable
In all modes, ROMON is forced to one out of reset. Writable once in normal modes and
writable at any time in special modes.
0 = ROM removed from the memory map
1 = ROM present in the memory map
Mode
IRVNE Out
of Reset
E Clock Out
of Reset
IRV Out of
Reset
IRVNE
Affects Only
Single-Chip
0
On
Off
E
Expanded
0
On
Off
IRV
Boot
0
On
Off
E
Special Test
1
On
IRV
CONFIG — System Configuration
$003F
Bit 7
654321
Bit 0
00000
NOCOP
ROMON
0
RESET:
00000
—
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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