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參數(shù)資料
| 型號： | MC68HC11D3CFB1 |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, QFP-44 |
| 文件頁數(shù)： | 74/124頁 |
| 文件大?。?/td> | 6875K |
| 代理商： | MC68HC11D3CFB1 |
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RESETS AND INTERRUPTS
TECHNICAL DATA
5-9
5.4.1 Interrupt Recognition and Register Stacking
An interrupt can be recognized at any time after it is enabled by its local mask, if any,
and by the global mask bit in the CCR. Once an interrupt source is recognized, the
CPU responds at the completion of the instruction being executed. Interrupt latency
varies according to the number of cycles required to complete the current instruction.
When the CPU begins to service an interrupt, the contents of the CPU registers are
pushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked,
the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The inter-
rupt vector for the highest priority pending source is fetched, and execution continues
at the address specified by the vector. At the end of the interrupt service routine, the
return from interrupt instruction is executed and the saved registers are pulled from the
stack in reverse order so that normal program execution can resume. Refer to SEC-
TION 3 CENTRAL PROCESSING UNIT for further information.
Table 5-4 Interrupt and Reset Vector Assignments
Vector Address
Interrupt Source
CCR Mask
Local
Mask
FFC0, C1 — FFD4, D5
Reserved
—
FFD6, D7
SCI Serial System
I Bit
—
SCI Transmit Complete
TCIE
SCI Transmit Data Register Empty
TIE
SCI Idle Line Detect
ILIE
SCI Receiver Overrun
RIE
SCI Receive Data Register Full
RIE
FFD8, D9
SPI Serial Transfer Complete
I Bit
SPIE
FFDA, DB
Pulse Accumulator Input Edge
I Bit
PAII
FFDC, DD
Pulse Accumulator Overflow
I Bit
PAOVI
FFDE, DF
Timer Overflow
I Bit
TOI
FFE0, E1
Timer Input Capture 4/Output Compare 5
I Bit
I4/O5I
FFE2, E3
Timer Output Compare 4
I Bit
OC4I
FFE4, E5
Timer Output Compare 3
I Bit
OC3I
FFE6, E7
Timer Output Compare 2
I Bit
OC2I
FFE8, E9
Timer Output Compare 1
I Bit
OC1I
FFEA, EB
Timer Input Capture 3
I Bit
IC3I
FFEC, ED
Timer Input Capture 2
I Bit
IC2I
FFEE, EF
Timer Input Capture 1
I Bit
IC1I
FFF0, F1
Real Time Interrupt
I Bit
RTII
FFF2, F3
IRQ (External Pin)
I Bit
None
FFF4, F5
XIRQ Pin
X Bit
None
FFF6, F7
Software Interrupt
None
FFF8, F9
Illegal Opcode Trap
None
FFFA, FB
COP Failure
None
NOCOP
FFFC, FD
Clock Monitor Fail
None
CME
FFFE, FF
RESET
None
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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