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參數(shù)資料
| 型號： | MC68HC11D3CFB1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 126/131頁 |
| 文件大小： | 1640K |
| 代理商： | MC68HC11D3CFB1 |
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MOTOROLA
TIMING SYSTEM
MC68HC11D3
9-8
TECHNICAL DATA
All TOCx register pairs reset to ones ($FFFF)
TI4/O5 — Timer Input Capture 4/Output Compare 5
$001E, $001F
Refer to 9.2.3 Timer Input Capture 4/Output Compare 5 Register.
9.3.2 Timer Compare Force Register
The CFORC register allows forced early compares. FOC[1:5] correspond to the five
output compares. These bits are set for each output compare that is to be forced. The
action taken as a result of a forced compare is the same as if there were a match be-
tween the OCx register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their programmed pin
actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is pro-
grammed to toggle its output on a successful compare because a normal compare that
occurs immediately before or after the force can result in an undesirable operation.
FOC1–FOC5 — Write Ones to Force Compare(s)
0 = Not affected
1 = Output x action occurs
Bits [2:0] — Not implemented, always read zero
9.3.3 Output Compare Mask Registers
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1
compare. The bits of the OC1M register correspond to PA[7:3].
TOC1–TOC4 — Timer Output Compare
$0016–$001D
$0016
Bit 15
14
13
12
11
10
9
Bit 8
TOC1 (High)
$0017
Bit 7
654321
Bit 0
TOC1 (Low)
$0018
Bit 15
14
13
12
11
10
9
Bit 8
TOC2 (High)
$0019
Bit 7
654321
Bit 0
TOC2 (Low)
$001A
Bit 15
14
13
12
11
10
9
Bit 8
TOC3 (High)
$001B
Bit 7
654321
Bit 0
TOC3 (Low)
$001C
Bit 15
14
13
12
11
10
9
Bit 8
TOC4 (High)
$001D
Bit 7
654321
Bit 0
TOC4 (Low)
CFORC — Timer Compare Force
$000B
Bit 7
654321
Bit 0
FOC1
FOC2
FOC3
FOC4
FOC5
0
RESET:
00000000
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