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參數(shù)資料
| 型號： | MC68HC11D0CFNE3 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 65/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 3MHZ 44-PLCC |
| 標準包裝： | 26 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 3MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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RESETS AND INTERRUPTS
TECHNICAL DATA
5-1
SECTION 5
RESETS AND INTERRUPTS
Resets and interrupt operations load the program counter with a vector that points to
a new location from which instructions are to be fetched. A reset immediately stops
execution of the current instruction and forces the program counter to a known starting
address. Internal registers and control bits are initialized so the MCU can resume ex-
ecuting instructions. An interrupt temporarily suspends normal program execution
while an interrupt service routine is being executed. After an interrupt has been ser-
viced, the main program resumes as if there had been no interruption.
5.1 Resets
There are four possible sources of reset. Power-on reset (POR) and external reset
share the normal reset vector. The computer operating properly (COP) system and the
clock monitor each has its own vector.
5.1.1 Power-On Reset
A positive transition on VDD generates a power-on reset (POR), which is used only for
power-up conditions. POR cannot be used to detect drops in power supply voltages.
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes active allows the
clock generator to stabilize. If RESET is at logical zero at the end of 4064 tCYC, the
CPU remains in the reset condition until goes to logical one.
It is important to protect the MCU during power transitions. Most M68HC11 systems
need an external circuit that holds the RESET pin low whenever VDD is below the min-
imum operating level. This external voltage level detector, or other external reset cir-
cuits, are the usual source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts. Refer to Figure 2-3.
5.1.2 External Reset (RESET)
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic one in less than two E-clock cycles after an inter-
nal device releases reset. When a reset condition is sensed, the RESET pin is driven
low by an internal device for four E-clock cycles, then released. Two E-clock cycles
later it is sampled. If the pin is still held low, the CPU assumes that an external reset
has occurred. If the pin is high, it indicates that the reset was initiated internally by ei-
ther the COP system or the clock monitor. It is not advisable to connect an external
resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices be-
cause the circuit charge time constant can cause the device to misinterpret the type of
reset that occurred.
5.1.3 COP Reset
The MCU includes a COP system to help protect against software failures. When the
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC68HC11D0CFNE3R | 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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| MC68HC11D0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC11D0FNR2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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