MOTOROLA
10-2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
TECHNICAL DATA
10
Figure 10-1 Programming Model
10.1.3 Index Register Y (IY)
The 16-bit IY register is also used for indexed mode addressing similar to the IX reg-
ister; however, all instructions using the IY register require an extra byte of machine
code and an extra cycle of execution time since they are two byte opcodes.
10.1.4 Stack Pointer (SP)
The stack pointer (SP) is a 16-bit register that contains the address of the next free
location on the stack. The stack is configured as a sequence of last-in-first-out read/
write registers which allow important data to be stored during interrupts and subroutine
calls. Each time a new byte is added to the stack (a push instruction), the SP is dec-
rement; whereas, each time a byte is removed from the stack (a pull instruction) the
SP is incremented.
10.1.5 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruc-
tion to be executed.
10.1.6 Condition Code Register (CCR)
The condition code register is an 8-bit register in which each bit signifies the results of
the instruction just executed. These bits can be individually tested by a program and
a specific action can be taken as a result of the test. Each individual condition code
register bit is explained below.
8-BIT ACCUMULATORS A & B
OR 16-BIT DOUBLE ACCUMULATOR D
7
15
0
7
0
0
A
B
D
IX
IY
SP
PC
7
0
C
V
Z
N
I
H
X
S
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
CONDITION CODES