參數資料
型號： MC68HC11A1MFU2
廠商： ABILIS SYSTEMS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數： 22/158頁
文件大?。?/td> 3803K
代理商： MC68HC11A1MFU2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
10-20
TECHNICAL DATA
10
6-7
LDY
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
(IX) + Offset
(IX) + Offset + 1
1
Opcode (Page Select Byte)
($1A)
Opcode (Second Byte) ($EE)
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
6-8
STD, STS, STX
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
(IX) + Offset + 1
1
0
Opcode
Index Offset
Irrelevant Data
Register Data (High Byte)
Register Data (Low Byte)
6-9
STY
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
(IX) + Offset
(IX) + Offset + 1
1
0
Opcode (Page Select Byte)
($1A)
Opcode (Second Byte) ($EF)
Index Offset
Irrelevant Data
Register Data (High Byte)
Register Data (Low Byte)
6-10
ADDD, CPX, SUBD
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
(IX) + Offset + 1
$FFFF
1
Opcode
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
6-11
CPD, CPY
7
1
2
3
4
5
6
7
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
(IX) + Offset
(IX) + Offset + 1
$FFFF
1
Opcode (Page Select Byte)
Opcode (Second Byte)
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
6-12
JSR
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Stack Pointer
Stack Pointer – 1
1
0
Opcode ($AD)
Index Offset
Irrelevant Data
First Opcode in Subroutine
Return Address (Low Byte)
Return Address (High Byte)
6-13
BCLR, BSET
7
1
2
3
4
5
6
7
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Opcode Address + 2
$FFFF
(IX) + Offset
1
0
Opcode
Index Offset
Irrelevant Data
Original Operand Data
Mask Byte
Irrelevant Data
Result Operand Data
6-14
BRCLR, BRSET
7
1
2
3
4
5
6
7
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
Opcode Address + 2
Opcode Address + 3
$FFFF
1
Opcode
Index Offset
Irrelevant Data
Original Operand Data
Mask Byte
Branch Offset
Irrelevant Data
Table 10-6 Cycle-by-Cycle Operation — Indexed X Mode (Sheet 2 of 2)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
*The reference number is given to provide a cross-reference to Table 10-1.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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PDF描述
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MC68HC11A1MP 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDIP48
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相關代理商/技術參數
參數描述
MC68HC11A1MP 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers
MC68HC11A1MP2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller
MC68HC11A1P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers
MC68HC11A1VFN 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontrollers
MC68HC11A1VFN2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller
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