參數(shù)資料
型號： MC68HC08QY2CDWE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-013AA, SOIC-16
文件頁數(shù)： 26/178頁
文件大小： 2311K
代理商： MC68HC08QY2CDWE
Functional Description
MC68HC08QY/QT Family Data Sheet, Rev. 1
Freescale Semiconductor
121
Figure 14-2. TIM Block Diagram
14.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 14.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
PRESCALER
PRESCALER SELECT
16-BIT COMPARATOR
PS2
PS1
PS0
16-BIT COMPARATOR
16-BIT LATCH
MS0A
ELS0B
ELS0A
TOF
TOIE
16-BIT COMPARATOR
16-BIT LATCH
CHANNEL 0
CHANNEL 1
TRST
TSTOP
TOV0
CH0IE
CH0F
ELS1B
ELS1A
TOV1
CH1IE
CH1MAX
CH1F
CH0MAX
MS0B
INTE
RNAL
BUS
MS1A
INTERNAL
BUS CLOCK
INTERRUPT
LOGIC
PORT
LOGIC
INTERRUPT
LOGIC
INTERRUPT
LOGIC
PORT
LOGIC
(IF AVAILABLE)
16-BIT COUNTER
TCLK
TCNTH:TCNTL
TMODH:TMODL
TCH0H:TCH0L
TCH1H:TCH1L
TCH0
TCH1
TCLK
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