參數(shù)資料
型號: MC68HC08QT2MDWE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝: LEAD FREE, EIAJ, SOIC-8
文件頁數(shù): 20/176頁
文件大小: 1124K
代理商: MC68HC08QT2MDWE
System Integration Module (SIM)
MC68HC08QY/QT Family Data Sheet, Rev. 2
116
Freescale Semiconductor
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and
Figure 13-18 shows the stop mode recovery time from interrupt or break
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
Figure 13-17. Stop Mode Entry Timing
Figure 13-18. Stop Mode Recovery from Interrupt
13.8 SIM Registers
The SIM has two memory mapped registers.
13.8.1 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
Bit 7
65
4321
Bit 0
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
Write:
POR:
100
00000
= Unimplemented
Figure 13-19. SIM Reset Status Register (SRSR)
STOP ADDR + 1
SAME
ADDRESS BUS
DATA BUS
PREVIOUS DATA
NEXT OPCODE
SAME
STOP ADDR
SAME
R/W
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
BUSCLKX4
INTERRUPT
ADDRESS BUS
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
STOP RECOVERY PERIOD
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