
MC68HC08AS32A — Rev. 1.1
Data Sheet
Freescale Semiconductor
31
$FE0F
LVI STATUS REGISTER (LVISR)
$FE10
EEPROM-EEDIVH NON-VOLATILE REGISTER (EEDIVHNVR)
$FE11
EEPROM-EEDIVL NON-VOLATILE REGISTER (EEDIVLNVR)
$FE12
RESERVED
↓
$FE19
$FE1A
EEPROM-EEDIVH REGISTER (EEDIVH)
$FE1B
EEPROM-EEDIVL REGISTER (EEDIVL)
$FE1C
EEPROM NON-VOLATILE REGISTER (EENVR)
$FE1D
EEPROM CONTROL REGISTER (EECR)
$FE1E
RESERVED
$FE1F
EEPROM ARRAY CONFIGURATION REGISTER (EEACR)
$FE20
MONITOR ROM
224 BYTES
↓
$FEFF
$FF00
UNIMPLEMENTED
↓
$FFD9
$FFDA
USER DEFINED VECTORS
38 BYTES
↓
$FFFF
Figure 2-1. Memory Map (Continued)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0000
Port A Data Register
(PTA)
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Write:
Reset:
Unaffected by reset
$0001
Port B Data Register
(PTB)
Read:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Write:
Reset:
Unaffected by reset
$0002
Port C Data Register
(PTC)
Read:
0
PTC4
PTC3
PTC2
PTC1
PTC0
Write:
Reset:
Unaffected by reset
$0003
Port D Data Register
(PTD)
Read:
0
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Write:
Reset:
Unaffected by reset
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Register (Sheet 1 of 8)