- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45223 > MC68HC05V7CFU (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC05V7CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 11/170頁(yè) |
| 文件大?。?/td> | 980K |
| 代理商： | MC68HC05V7CFU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)
MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 94
MC68HC05V7 Specification Rev. 1.0
15.1.2.2
Reset
This mode is entered from the Power Off mode whenever the MCU supply voltage VDD
rises above the minimum specified value and some MCU reset source is asserted. In order
to prevent an unknown state from being entered and to guarantee correct operation, the
internal MCU reset will be asserted while the MDLC module is being powered up.
This mode is entered from any other mode whenever the MCU supply voltage VDD drops
below the minimum value for correct MDLC operation. When this occurs, the MDLC module
will reenter the Reset mode before being powered down to prevent an unknown state from
being entered.
The Reset mode is also entered from any other mode as soon as one of the MCU’s possible
reset sources (for example, POR, COP watchdog, Reset pin etc.) is asserted.
In this mode, the internal MDLC voltage references are operative, VDD is supplied to the
internal circuits, which are held in their reset state and the internal MDLC system clock is
running. Registers will assume their reset condition. Outputs are held in their programmed
reset state, inputs and network activity are ignored.
15.1.2.3
Run
This mode is entered from the Reset mode after all MCU reset sources are no longer
asserted. It is entered from the MDLC Wait mode whenever a message is successfully
received.
It is entered from the MDLC Stop mode whenever network activity is sensed though
messages will not be received properly until the clocks have stabilized and the CPU is also
in the Run mode.
In this mode, normal network operation takes place. The user should ensure that all MDLC
transmissions have ceased before exiting this mode.
15.1.2.4
MDLC Wait
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a WAIT instruction and if the WCM bit in the MCR register is previously
cleared.
In this mode, the MDLC internal clocks continue to run but the physical interface circuitry is
placed in a low power mode and awaits a valid network message. If a valid network
message is successfully received (RXMS=1) a CPU interrupt request will be generated.
15.1.2.5
MDLC Stop
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM
bit in the MCR register is previously set.
In this mode, the MDLC internal clocks are stopped but the physical interface circuitry is
placed in a low power mode and awaits network activity. If network activity is sensed, then
a CPU interrupt request will be generated, restarting the MDLC internal clocks.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05X16FU | 8-BIT, MROM, MICROCONTROLLER, PQFP64 |
| MC68HC705X32FU | 8-BIT, OTPROM, MICROCONTROLLER, PQFP64 |
| MC68HC05X16MFU | 8-BIT, MROM, MICROCONTROLLER, PQFP64 |
| MC68HC05X32FU | 8-BIT, MROM, MICROCONTROLLER, PQFP64 |
| MC68HC705X32CFU4 | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05X16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor HCMOS) microcontroller unit |
| MC68HC05X32 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor HCMOS) microcontroller unit |
| MC68HC05X4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05X4CDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05X4DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。